This invention relates to asynchronous shift registers and more particularly to an improvement which permits data from a data source to be gated directly into that empty stage of the shift register that is nearest the output stage and has no full stage preceding it.
Asynchronous shift registers, also known as first-in first-out registers, are well known in the art and are frequently employed between a data source which supplies data to the shift register at one speed and a data sink which intermittently takes data from the shift register at another speed. A typical asynchronous shift register of the prior art is shown in U.S. Pat. No. 3,166,715 to Cogar. As exemplified by the patent to Cogar, it has been conventional in the prior art to supply all data from the data source to the first stage of the asynchronous shift register and to take data from the last or output stage of the shift register. Thus, each bit of data entered into the shift register must be successively shifted through all of the stages before it reaches the output stage. The shift registers may be quite long and frequently many of the stages nearest the input stage are empty at the time a bit of data is applied to the first stage. Obviously, this causes an undue delay in making the bit of data available at the output stage since it must be shifted through all of the empty stages.